1. Field of the Invention
The present invention generally relates to a semiconductor device, and in particular to a semiconductor device having a circuit construction operating on the basis of a clock signal applied from an external portion.
2. Description of the Prior Art
In accordance with the development of recent information devices, a semiconductor device has been also developed, as a prerequisite condition for satisfying portability particularly for a lap top computer, a portable terminal device and the like, an operation of a higher speed, with a lower consuming power and a lower voltage is required.
However, it is not easy to satisfy two prerequisite conditions of higher speedy operation and lower consuming power, and various developments of technologies have been performed.
Especially, in a dynamic random access memory (hereinafter, referred to as DRAM), a variety of technological developments have been performed, recently, and a synchronous DRAM (hereinafter, referred to as SDRAM) which is operable in synchronization with a high speed clock signal over 100 MHz of frequency from the external.
Moreover, conventionally SDRAM has performed inputting and outputting data corresponding to a rise of a clock signal, however, DDR (Double Data Rate) SDRAM performing the data input and output at both rise and fall timings of a clock signal has been also developed.
In order to realize a DDR SDRAM, it is necessary to suppress deviation of a timing is caused due to external factors such as temperature of a semiconductor device, variation of power voltage, process dispersion and the like.
Particularly, for an internal clock signal used inside of a semiconductor device in synchronized with the external clock signal, it is important to suppress an occurrence of a jitter and variation in frequency, and therefore a DLL (Delay Locked Loop) circuit is introduced.
A DLL circuit controls an amount of delay of an internal clock signal, so that a time difference with respect to the external clock signal can be made constant and data outputting can be performed both in a rise and a fall of a high speed clock signal.
Although a DDR SRAM has been exemplified as described above, in order to correspond to portable devices and the like despite of acceleration in technology, consuming current must be reduced in each operating state of semiconductor devices including not only SDRAM but also other devices operating in synchronized with an external clock signal.
However, in each operating state, under the present circumstances, it is difficult to suppress consuming current in consideration of satisfying stability and acceleration of an operation.
Moreover, particularly in a DDR SDRAM, although there are a plurality of operating states, recently, in a state of a power down mode where a command made by combination of control signals from the external is not inputted, the reduction of consuming current in the power down mode has been strongly required.
However, in order to stably hold data in a memory cell even in the power down mode, and in order to enable a higher operation even in the case where the power down mode is changed into the usual operation mode, a variety of circuits such as an internal step-down circuit, a substrate bias circuit, a word line boost circuit, a refresh circuit, a DLL circuit and the like are made be operated constantly.
Therefore, the suppression of consuming current in the power down mode has been difficult.
However, in consideration of adaptation to portable devices and the like, the suppression of consuming current in the power down mode has been an important task in DDR SDRAM and the like.
An essential object of the present invention is to solve the above described problem and to provide a semiconductor device capable of reducing consuming current while prerequisite conditions for such as stability of an operation and the like are satisfied in a specified operating condition.
Further, it is another object to provide a semiconductor device capable of reducing consuming current while the prerequisite conditions for such as the stability of an operation and the like are satisfied in the power down mode of DDR SDRAM and the like.
According to a first aspect of the present invention, a semiconductor device comprises: a clock generation unit generating an internal clock signal based on an external clock signal; a clock synchronization unit adapted to operate in synchronization with the internal clock signal; and a control unit adapted to activate the clock generation unit for a specific time period when the clock synchronization unit is in a state of inactivation.
According to a second aspect of the present invention, an input signal to the control unit is produced based on an external input signal and the control unit generates a control signal for controlling activation or inactivation of the clock generation unit in accordance with the input signal.
According to a third aspect of the present invention, when the clock synchronization unit is in a state of inactivation, the control signal for activating the clock generation unit is generated by the control unit based on the external input signal which is a pulse signal.
According to a fourth aspect of the present invention, the input signal to the control unit is a first pulse signal which is produced based on the external input pulse signal and the control unit generates a second pulse signal as the control signal for activation of the clock generation unit wherein the second pulse signal has its rise or fall delayed with respect to a rise or fall of the first pulse signal.
According to a fifth aspect of the present invention, a start of the second pulse signal is based on a change of the first pulse signal and an end of the second pulse signal is based on a fact that a third pulse signal which is generated in the control unit based on the first pulse signal reaches a specified number of pulses.
According to a sixth aspect of the present invention, a start of the second pulse signal is based on a fact that a third pulse signal which is generated in the control unit based on the first pulse signal reaches a first specified pulse number and an end of the second pulse signal is based on a fact that the third pulse signal reaches a second specified pulse number which is larger than the first specified pulse number.
According to a seventh aspect of the present invention, when the third pulse signal reaches a third pulse number which is larger than that the second pulse number, the pulse number of the third pulse signal is reset, and the pulse number of the third pulse signal is again increased to reach to the first and second pulse numbers, whereby the second pulse signal is periodically generated.
According to an eighth aspect of the present invention, the control unit includes a ring oscillator generating the third pulse signal and a counter counting a pulse number of the third pulse signal.
According to a ninth aspect of the present invention, the control unit includes a ring oscillator generating the third pulse signal, a counter counting a pulse number of the third pulse signal and a logic circuit outputting a designation signal designating a start of the second pulse signal when the counter reaches the first pulse number and outputting a designation signal designating an end of the second pulse signal when reaching the second pulse number.
According to a tenth aspect of the present invention, the control unit further receives another internal clock signal inputted thereto which is produced based on another external clock signal, and wherein a start of the second pulse signal is based on a change of the first pulse signal and an end of the second pulse signal is based on a fact that the another internal clock signal reaches a specified pulse number.
According to an eleventh aspect of the present invention, the control unit includes a counter counting a pulse number of the another internal clock signal.
According to a twelfth aspect of the present invention, the control unit includes a shift resistor which is controlled by another internal clock signal produced based on an external clock signal, and wherein a start of the second pulse signal is based on a change of the first pulse signal and an end of the second pulse signal is based on the first pulse signal which has passed through the shift resistor.
According to a thirteenth aspect of the present invention, the clock generation unit includes a delay locked loop circuit.
In this construction, the clock generation unit may make an input signal of the delay locked loop circuit a fixed signal before and after the clock generation unit is activated during the specific time period.
The semiconductor device may include a dynamic random access memory, and the clock synchronization unit includes an output circuit of read data of the dynamic random access memory.
In this construction, the input signal of the control unit produced based on the external input signal is a clock enable signal for designating an input of an external signal for controlling an operation of the dynamic random access memory.
An inactivated state of the output circuit of the read data may be a power down mode of the dynamic random access memory.
The specific time period for activating the clock generation unit may include an auto refresh time period of the dynamic random access memory.
The input signal of the control unit produced based on the external input signal may be an auto refresh designation signal.
The input signal of the control unit produced based on the external input signal may be a signal for activating a read operation.
The specific time period for activating the clock generation unit may be made less than one-tenth of a time period of a power down mode.